Indian Journal of Advancd Research in Electrical, Electronics and Instumentation Engineering (IJAREEIE)- Vol.2 No.1 2014

1. An Improved Low Latency Systolic Structured Galois Field Multiplier
M.Rajendran and M.Rajendran
Full Text Paper    Pages: 1-6

2. Fault Secure Memory Design Using Difference-Set Codes For Memory Applications
Lakshmanan.V and Vijaya Ganesh.J
Full Text Paper    Pages: 7-14

3. Automaticfire Sensing And Controllinginformation Systeminatrain Using Plc And Scada Networks.
Sathish.R, Ramakrishnan.V and Erachappan.R
Full Text Paper    Pages: 15-18

4. A Dvr Built With A 7 Level Cascade Asymmetric Multilevel Converter
S.SriKrishnakumar,B.S.Dharshana,P.HelenChandrika and S.Hemalatha
Full Text Paper    Pages: 19-25

5. Design And Implementation of PMSG Conversion System Using Statcom Model
K.MadhuBala and D.Saravanan
Full Text Paper    Pages: 26-32

6. Implementation Of Boost Converter With Voltage Multiplier Module For A Photovoltaic System
R.Karthikeyan and K.Gobi
Full Text Paper    Pages: 33-38

7. Deciding Optimal Location For Placing Facts Devices [UPFC, IPQC, DPFC] Using Bang-Bang Control Technique
R.Venkatesh, M. Rekha and G. Sundar
Full Text Paper    Pages: 39-45

8. Standard Cell Based Anti fuse FPGA
Gokulakrishnan Shanmugam and Prof.S.Ramaratnam
Full Text Paper    Pages: 46-48